Nonvolatile semiconductor memory transistors are roughly divided to the FG (Floating Gate) type wherein charge storing means (floating gate) for holding charges is continuing flatly and, for example, the NOMOS (Metal-Oxide-Nitride-Oxide Semiconductor) type wherein charge storing means (a charge trap, etc.) are dispersed flatly.
In a FG type nonvolatile memory transistor, a first dielectric film, a floating gate FG made of polysilicon, etc., a second dielectric film made by for example an ONO (Oxide-Nitride-Oxide) film, and a control gate are successively stacked on a semiconductor substrate or a well.
In a MONOS type nonvolatile memory transistor, a first dielectric film, a nitride film [SixNy (0<x<1, 0<y<1)] mainly operating charge storage, a second dielectric film and a gate electrode are successively stacked on a semiconductor substrate or a well.
In the MONOS type nonvolatile memory transistor, carrier traps as charge storing means are spatially (namely, in the plane direction and the film thickness direction) dispersed and spread in the nitride film or near a boundary of the second dielectric film and the nitride film. Due to this, charge retention property depends on an energetic or spatial distribution of charges caught by the carrier traps in the nitride film besides the film thickness of the first dielectric film.
When a partial leakage current path caused by a defect, etc. arises in the first dielectric film, a large amount of stored charges leak through the leakage path to the substrate side and the charge retention property easily declines in the FG type memory transistor. On the other hand, in the MONOS type memory transistor, since the charge storing means are spatially dispersed, only a part of stored charge around the leakage path partially leaks through the leakage path and the charge retention property of the memory transistor as a whole is hard to decline. Therefore, the problem of declining charge retention property due to the first dielectric film getting thinner is not as serious in the MONOS type memory transistor as in the FG type memory transistor.
Nonvolatile memory apparatuses are roughly divided to the known stand-alone type and logical circuit embedded type. In the stand-alone type, a nonvolatile memory transistor is used as a memory element of a dedicated memory IC. In the logical circuit embedded type, a memory block and a logical circuit block are provided as a core of a system-on-chip, and a nonvolatile memory transistor is used as a memory element for storing data in a nonvolatile way in the memory block.
A one-memory transistor type memory cell is used in many of nonvolatile memory apparatuses of the logical circuit embedded type.
As a typical example of a one-memory transistor cell of the FG type, an ETOX cell of the Intel Corporation is known. A common source type memory cell array system wherein sources are shared is adopted at the time of an array arrangement of the ETOX cell.
A one-memory transistor cell of the MONOS type has gathered attention from the viewpoint that a cell area can be reduced and a low voltage is easily attained. As a typical example thereof, a high density memory cell called NROM of Saifun Semiconductors Ltd. is known. The NROM cell uses dispersed carrier traps as the charge storing means, so data storage of two-bit/cell is possible by performing charge injection respectively to two different regions in a cell. When laying out an array arrangement of the NROM cells, an impurity diffusion layer is shared by adjacent cells in the row direction, and when storing or reading two-bit data, a virtual ground array system wherein a function of the impurity diffusion layer is switched by a source and a drain for use is adopted.
When writing data to an ETOX cell and MROM cell, the channel hot electron (CHE) injection is used, by which a low voltage is easily attained comparing with the FN tunnel injection. In the CHE injection writing, an electric field is applied between the source and drain, electrons supplied from the source side to the channel are energetically excited at a drain side end of the channel, and hot electrons are generated. Hot electrons beyond a height of an energy barrier (3.2 eV in the case of a silicon dioxide film) of the first dielectric film are injected to the charge storing means (floating gate or carrier trap).
However, in the CHE injection writing of the FG type memory cell, a voltage of 10V or more has to be applied to the gate for exciting electrons to a degree of over the high energy barrier of 3.2eV. Although the writing gate voltage is lower comparing with the case of FN tunnel writing requiring a voltage of 18V or more, it is rather high comparing with a power source voltage of 2.5V to 5.0V. A gate application voltage at the time of the CHE injection writing of a MONOS type memory cell is lower than the gate application voltage at the time of the CHE injection writing of the FG type memory cell, but it is higher than the power source voltage. For example, in the case of a NROM, a gate application voltage required at the time of data writing is 9V.
Therefore, regardless of being the FG type or MONOS type, it is necessary to generate a writing gate voltage by raising the power source voltage by a booster circuit in memory peripheral circuits.
In a booster circuit and a circuit for applying a writing gate voltage after boosting in the memory peripheral circuits, a high withstand voltage transistor is necessary. The high withstand voltage transistor has a low commonality with other transistors for a power source voltage in the memory peripheral circuits and a logic transistor in the logical circuit block. Therefore, a process exclusive to the high withstand voltage transistor is necessary, which hinders a reduction of production cost of a logical circuit embedded type memory IC.